A technique for Improving dual-output domino logic

We present a technique, termed clockgenerating (CG) domino, for improving dual-output domino logic that reduces area, clock load, and power without increasing the delay. A delayed clock, generated from certain dual-output gates, is used to convert other dual-output gates to single output. Simulation results with ISCAS 85 benchmark circuits indicate an average reduction in area, clock load, and power of 17%, 20%, and 24% respectively over dual-output domino and a 48% power reduction for the largest circuit. Keywords— Domino Logic, Delayed Clocks, Low-power